1. Technical Field
The present invention relates to parallel processing and, in particular, to semi-automatic restructuring of offloadable tasks for accelerators.
2. Description of the Related Art
The Many Integrated Core (MIC) architecture is an x86-compatible, many-core co-processor aimed at accelerating applications written for multi-core processors. Parallel code regions are offloaded to MIC for execution using, e.g., #pragma directives. When a code region is offloaded, execution on the CPU is suspended until the offloaded code section executes to completion.
In the most common usage model, highly parallel code regions in an application are offloaded to MIC. The developer identifies and marks such code regions using a directive called #pragma offload. Data transfers between the host and coprocessor are specified using in/out/inout clauses. The goal of MIC is to improve overall application performance by taking advantage of higher number of cores. Although MIC is a step forward in terms of programmability compared to GPUs, a certain amount of developer effort is needed to obtain good performance gains.